The present invention relates to the field of integrated circuits in general, and more particularly, to the fabrication of self-aligned features of integrated circuits.
Transistors, such as Metal Oxide Semiconductor Field Effect Transistors (MOSFET devices) are commonly used to provide switching functions in integrated circuits. For example, when the MOSFET device is on, current flows in a channel between the source and the drain of the MOSFET device. Ideally, when the MOSFET device is off, no current flows in the channel. In practice, however, a small leakage current may flow in the channel when the MOSFET device is off.
To increase the performance and density of integrated circuits, the size of the MOSFET devices used to fabricate the integrated circuits may be reduced. Unfortunately, decreasing the size of the MOSFET devices may shorten the channel length thereby possibly inducing performance problems known as xe2x80x9cshort channel effects.xe2x80x9d For example, when the channel length is reduced to about 80 nanometers (nm) or less the leakage current of the MOSFET device may be increased such that the MOSFET device may not function properly (i.e., it may be difficult to turn the MOSFET device off).
It is known to form a double gate MOSFET to reduce the short channel effects described above. In particular, a self-aligned double gate MOSFET may be formed using lateral epitaxy. One type of conventional lateral epitaxy used to form self-aligned double ate transistors is discussed in U.S. Pat. No. 5,646,058 to Taur et al. entitled xe2x80x9cMethod or Fabricating A Self-Aligned Double-Gate MOSFET By Selective Lateral Epitaxyxe2x80x9d which is incorporated herein by reference. Unfortunately, tunnel epitaxy may not be well suited for some manufacturing processes.
It is also known to form self-aligned double gate MOSFETs using a transparent quartz xe2x80x98handlexe2x80x99 wafer with an ion cut technique. One such conventional technique is discussed in xe2x80x9cInvestigation of a Novel Self-Aligned Dual Gate MOSFET Structurexe2x80x9d by B. E. Roberds et al., Proceedings 1998 IEEE International SOI Conference, Oct. 1998. Unfortunately, a process using quartz materials may be difficult to implement because the quartz make break easily. Moreover, short wavelength light (used, for example, to create devices having small dimensions) may be absorbed by the quartz, thereby possibly reducing the accuracy of patterning through quartz. Accordingly, there continues to exist a need to improve the fabrication of self-aligned double gate MOSFETs.
In view of the above, it is an object of the present invention to allow improvement in the fabrication of self-aligned features of integrated circuits.
It is another object of the present invention to allow improvement in the fabrication of self-aligned double gate transistors.
It is a further object of the present invention to allow improved devices having self-aligned features.
These and other objects of the present invention are provided by forming an upper gate electrode on an integrated circuit substrate and modifying a buried layer in the integrated substrate using the upper gate electrode as a mask. The modified buried layer is used to form a lower gate electrode on the integrated circuit substrate, wherein the lower gate electrode is self-aligned to the modified buried layer. Accordingly, standard fabrication techniques, such as ion implantation, etching, and wafer bonding may be used to fabricate a self-aligned double gate transistor according to the present invention. Moreover, the present invention may be utilized to form any self-aligned double sided features of integrated circuits such as contacts and vias.
In another aspect of the present invention, the lower gate electrode is self-aligned to the upper gate electrode. In one embodiment, the present invention is used to fabricate a self-aligned double gate MOSFET, wherein the self-alignment of the upper and lower gate electrodes may reduce some of the short channel effect associated with conventional approaches. The self-alignment of the upper and lower gate electrodes may also reduce a parasitic capacitance that can be caused by misalignment of upper and lower gate electrodes.
In another aspect of the present invention, electrically inactive ions are implanted to modify the buried layer. The ion implantation may modify the buried layer to form a modified buried layer at an interface of the integrated circuit substrate and the buried layer. Alternately, the modified buried layer is formed underlying the interface of the buried layer and the integrated circuit substrate.
The lower gate electrode can be formed by etching a lower surface of the integrated circuit substrate using the modified buried layer to form a cavity therein. A gate material is formed in the cavity. Alternately, the lower gate electrode can be formed by forming a dummy gate using the modified buried layer and replacing the dummy gate with the lower gate electrode by etching out the dummy gate to form a cavity and forming the gate material in the cavity.
In an unexpected aspect of the present invention, the drain, gate, and source electrodes of a transistor formed according to the present invention can be accessed from above and/or below the transistor. For example, a plurality of first conductive lines can be formed to provide interconnect to the lower surface of the gate, drain, and source electrodes of the transistor and a plurality of second conductive lines can be formed to provide interconnect to the upper surface of the gate, drain, and source electrodes of the transistor.
Accordingly, routing of conductive lines between transistors or in/out of the integrated circuit device can be accomplished by routing the conductive lines to the upper surface or the lower surface of the drain or source electrodes. Consequently, the routing of conductive lines in the integrated circuit may be simplified due to the reduced number and/or density, of the conductive lines electrically on the respective surface. For example, the conductive lines electrically coupled to the lower surface can provide power and ground voltages to the transistors while the conductive lines electrically coupled to the upper surface can provide for the connection of signals between transistors. Reducing the density of the conductive lines may allow the width of the conductive lines to be increased, thereby reducing the resistance of the conductive lines and reducing the delay associated with the conductive lines.
In a still a further unexpected aspect of the present invention, multiple integrated circuits according to the present invention can be stacked to form multiple layers of self-aligned double gate transistors. Each of the layers of self-aligned double gate transistors has a lower level of conductive lines which can provide electrical coupling between the transistors included in the same layer (i.e., intra-layer routing) and an upper layer of conductive lines which provide electrical coupling between layers of self-aligned double transistors (i.e., inter-layer routing). Accordingly, the layers of conductive lines can be dedicated to routing particular signals in the integrated circuit device.